ReQL command: bit_sal

Command syntax

r.bit_sal(number) → number
r.bit_sal(number[, number, ...]) → number

Description

In an arithmetic shift (also referred to as signed shift), like a logical shift, the bits that slide off the end disappear (except for the last, which goes into the carry flag). But in an arithmetic shift, the spaces are filled in such a way to preserve the sign of the number being slid. For this reason, arithmetic shifts are better suited for signed numbers in two’s complement format.

Note: SHL and SAL are the same, and differentiation only happens because SAR and SHR (right shifting) has differences in their implementation.

Example:

r.expr(5).bit_sal(4).run(conn)

# Result:
80